LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity freqm is
port(

	clk: 		in std_logic;
	gate: in std_logic;
	bclk: 	in std_logic;
	xclk1: 	in std_logic;
	clr: 		in std_logic;
	output1: out std_logic_vector(31 downto 0);
	output2: out std_logic_vector(31 downto 0);
	shiji_fre:out std_logic	

);
end freqm;

architecture bahave of freqm is
signal shiji: std_logic;
signal bz_count,dc_count,bz_chu,dc_chu: std_logic_vector(31 downto 0);
signal count1: integer range 0 to 100000000;

begin

DQ: process(clr,xclk1,gate)
begin
	if clr = '0' then shiji <= '0';
	elsif rising_edge(xclk1) then
		shiji <= gate;

	end if;
end process;

shiji_fre <= shiji;

bzcounter: process(clr,bclk,shiji)
begin
	if clr = '0' then bz_count <= (others => '0');
	elsif rising_edge(bclk) then
		if shiji = '1' then	
			bz_count <= bz_count + 1;
		else
			bz_count <= (others => '0');
		end if;
	end if;
end process;

dccounter: process(clr,xclk1,shiji)
begin
	if clr = '0' or shiji = '0' then dc_count <= (others => '0');
	elsif rising_edge(xclk1) then 
		if shiji = '1' then
			dc_count <= dc_count + 1;
		end if;
	end if;
end process;
		



process(shiji)
begin
	if (shiji'EVENT AND shiji = '0') then	
		dc_chu <= dc_count;
		bz_chu <= bz_count;
	end if;
end process;

process(dc_chu,bz_chu)
begin
	output1 <= dc_chu;
	output2 <= bz_chu;
end process;

end architecture;